A 1.8-V GPIO with Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology
IEEE JOURNAL OF SOLID-STATE CIRCUITS（2024）
Key words
Reliability,Logic gates,Integrated circuit reliability,Reliability engineering,High-voltage techniques,Transient analysis,Field effect transistors,Design and technology co-optimization (DTCO),design for reliability (DfR),dynamic gate bias (DGB),I/O buffer,level shifter,mixed-voltage tolerant,oxide reliability,reliability array
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