A Sub-1-V Capacitively-Biased Voltage Reference with an Auto-Zeroed Buffer and a TC of 18-Ppm/° C

Heungsik Eum,Kofi A. A. Makinwa,Inhee Lee,Youngcheol Chae

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS（2025）

Yonsei Univ | Delft Univ Technol | Univ Pittsburgh

Cited 0|Views6

Abstract

This brief presents a capacitively-biased CMOS voltage reference, which can operate from a sub-1V supply while achieving a low temperature coefficient (TC) and a competitive power-supply rejection ratio (PSRR). The reference voltage is generated by a capacitive bias circuit that provides a well-defined proportional-to-absolute-temperature (PTAT) bias current for a Delta Vth type reference that consists of two stacked MOSFETs with different threshold voltages. The generated output voltage is sampled by an auto-zeroed (AZ) buffer, which can drive capacitive loads up to 2 nF. Fabricated in a 65 nm CMOS process, the prototype voltage reference occupies 0.058 mm(2), including the AZ buffer and an on-chip timing generator. It outputs a reference voltage of 204.1 mV with a minimum supply voltage of 0.7 V. It achieves a TC of 18 ppm/degrees C from -40 degrees C to 85 degrees C and a PSRR of -75 dB at 100 Hz with only 200 mu V ripple.

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Key words

CMOS voltage reference,capacitively-bias circuit,sub-threshold voltage reference,CMOS analog design,sub-1-V,high-precision circuits

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