Intelligent Simulation Platform for Fault Injection to Configuration Bitstream Based on Multiple Cores Architecture Processor

The large scale digital circuit in space radiation is susceptible to single event upset caused by single event effect. It is particularly important to reinforce the FPGA from the perspective of reliability. The cost of conducting real irradiation experiments is too high and too expensive. Therefore, this paper proposes a SEM IP core based method to design an experimental and verification platform for simulating single event upset. This method performs bit-by-bit fault injection on the configuration bits in the user memory through SEM IP, and reads back to judge the consistency to verify the correctness of the method. The results show that the platform can inject faults accurately and quickly to meet the requirements of simulating space environment.