Special Session: Enhancing Reliability in Digital Computing-in-Memory Architectures Through Approximation and Fault Tolerance Methods

Shih-Hsu Huang, Chih-Li Hsiao, Wei-Che Cheng

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems（2024）

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Adder tree,Low power,In-memory-computing,Memory array,Redundancy design

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