V2Va +: an Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

Chao Wang, Yicong Shao,Jiajie Huang,Wangzilu Lu,Zhiwen Gu, Longfan Li,Yuhang Zhang,Jian Zhao,Wei Mao,Yongfu Li

IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS（2024）

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Translation,Codes,Runtime,Design methodology,Syntactics,Generators,Complexity theory,Hardware design languages,Engines,Digital circuits,Verilog-A,Verilog,SystemVerilog,mixed-signal simulation,abstract syntax tree,translator

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