Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells Via Source/Drain Doping Engineering
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY(2025)
关键词
Optimization,Gallium arsenide,Logic gates,MOS devices,Transistors,Silicon,Silicon germanium,Performance evaluation,Implants,Doping profiles,Gate-all-around nanosheet transistor (GAA NSFET),source/drain (S/D) doping,spacer,lightly doped drain (LDD),6T static random-access memory (6T-SRAM)
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