Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900μA/μm at Lg<50nm

W. Mortelmans, P. Buragohain, A. Kitamura,C.J. Dorow,C. Rogan, L. Siddiqui,R. Ramamurthy, J. Lux, T. Zhong, S. Harlson, E. Gillispie, T. Wilson, R. Toku,A. Oni,A. Penumatcha, M. Kavrik, M. Jaikissoon,K. Maxey, A. Kozhakhmetov, C-Y. Cheng, C-C. Lin, S. Lee, A. Vyatskikh,N. Arefin, D. Kencke, J. Kevek,T. Tronic,M. Metz,S.B. Clendenning,K.P. O'Brien,U. Avci

2024 IEEE International Electron Devices Meeting (IEDM)（2024）

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Key words

Gate Oxide,Device Performance,Nanosheets,Transition Metal Dichalcogenides,Monolayer MoS2,Gate Length,2D Transition Metal Dichalcogenides,Two-dimensional Transition Metal Dichalcogenides,2D Materials,Types Of Pain,Impact Scale,Atomic Layer Deposition,Device Output,Gate Capacitance,Atomic Layer Deposition Process,Scale Thickness,Gate Stack

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