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First Demonstration of BEOL Wafer-Scale All-ALD Channel CFETs Using IGZO and Te for Monolithic 3D Integration

Chang Niu,Pukun Tan,Jian-Yu Lin, Linjia Long,Zehao Lin, Yizhi Zhang,Haiyan Wang, Glen D. Wilk,Peide D. Ye

2024 IEEE International Electron Devices Meeting (IEDM)(2024)

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Abstract
In this work, we demonstrated for the first time Back-End-Of-Line (BEOL) compatible complementary field-effect transistors (CFETs) with wafer-scale all atomic-layer-deposited (ALD) channels for monolithic 3D integration. A p-type transistor based on Tellurium (Te)/Tellurium oxide (TeOx) heterostructure was fabricated on top of an InGaZnO (IGZO) n-type transistor using a common gate structure. An excellent IGZO device performance was achieved with an on-current (Ion) of $1\text{mA}/\mu\mathrm{m}$ at $\mathrm{V}_{\mathrm{d}\mathrm{s}}=1$ V in an enhancement-mode operation with a channel thickness $(\mathrm{T}_{\mathrm{c}\mathrm{h}}$) of 2 nm. The uniform wafer-scale growth of p-type semiconductor Te was achieved by introducing methanol in ALD process. Transistor arrays were measured on a four-inch wafer, demonstrating good uniformity and yield based on statistical electrical characterization. The ALD CFET-inverters were fabricated and confirmed by cross-sectional scanning transmission electron microscopy (STEM). They exhibit good electrical performance with a high gain of 116.5 V/V and a large noise margin of 2.2V (88%) at VDD = 5 V. The thermal budget of the entire ALD-CFET fabrication process is 225°C and BEOL compatible.
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Key words
Monolithic 3D,Monolithic 3D Integration,Fabrication Process,Heterostructures,Scanning Transmission Electron Microscopy,Electrical Performance,Channel Thickness,Energy-dispersive X-ray Spectroscopy,Elemental Mapping,Contact Resistance,Threshold Voltage,Transfer Characteristics,Channel Length,Oxide Semiconductor,Low-temperature Process,Probe Station,Dry Etching,Channel Material,Metal Gate,Vertical Stacking
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