Monolithic Stacked FET with Stepped Channels for Future Logic Technologies

Chen Zhang, SeungMin Song,Jay Strane, Lijuan Zou, Seungchan Yun, Keumseok Park, Abir Shadman, Jaehong Lee, WuKang Kim, Utkarsh Bajpai, Larry Zhuang, Shahrukh Khan, Wai Kin Li,Shogo Mochizuki,Takashi Ando,Shay Reboh, Debarghya Sarkar, Myung Yang, Myunghoon Jung,Tsung-Sheng Kang, Ilhom Saidjafar, Nate Putnam,Shanti Pancharatnam,Muthumanickam Sankarapandian, Erik Milosevic, Junmo Park, Kishwar Mashooq, Prabudhya R. Chowdhury, Jim Mazza, Nick Lanzillo, Sarah N. Chowdhury, Yeojin Lee,Paul Jamison, Matt Malley, Pinlei Chu, Jeonghyun Hwang, Mohsen Nasseri, Kibyung Park, Namkyu Cho, Jongmin Shin, Inwon Park, Thanh Nguyen, Beomjin Park, Feng Liu, Shivani Kumar, Cliff Osborn,Juntao Li, Lukas Tierney,James Demarest, Junli Wang,Eric Miller, Susan Fan, Jingyun Zhang, Yu Zhu,John Arnold,Tenko Yamashita,Dan Dechene,Kang-Ill Seo,Dechao Guo,Huiming Bu

2024 IEEE International Electron Devices Meeting (IEDM)（2024）

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Key words

Logic Technology,Aspect Ratio,Channel Width,Channel Bottom,Metal Work Function,Stack Height,Contact Resistance,Front Side,Cell Height,Metal Gate,Standard Height,Drain Contacts,Top Channel,Bottom Contact,Source Side,Uniform Design,Edge Contact

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