A 0.063 Μm2 FinFET SRAM Cell Demonstration with Conventional Lithography Using a Novel Integration Scheme with Aggressively Scaled Fin and Gate Pitch

V. S. Basker,T. Standaert, H. Kawasaki,C. -C. Yeh,K. Maitra,T. Yamashita,J. Faltermeier,H. Adhikari,H. Jagannathan,J. Wang,H. Sunamura,S. Kanakasabapathy,S. Schmitz,J. Cummings,A. Inada,C. -H. Lin,P. Kulkarni,Y. Zhu,J. Kuss, T. Yamamoto,A. Kumar,J. Wahl,A. Yagishita,L. F. Edge,R. H. Kim,E. Mclellan, S. J. Holmes, R. C. Johnson,T. Levin,J. Demarest,M. Hane,M. Takayanagi,M. Colburn,V. K. Paruchuri, R. J. Miller,H. Bu,B. Doris,D. McHerron,E. Leobandung,J. O'Neill

2010 Symposium on VLSI Technology（2010）

Cited 81|Views24

Key words

MOSFET,SRAM chips,nanopatterning,photolithography,semiconductor doping,FinFET SRAM cell demonstration,conformal doping,contacted gate pitch,differential fin pitch,double-etch sidewall image transfer process,double-expose sidewall image transfer process,epitaxial films,fin formation,gate-first metal gate stacks,integration scheme,optical lithography,patterning scheme,short channel control,size 25 nm,size 40 nm,size 80 nm,transistors

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