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17.2 5.6mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560mv Utilizing Small-Signal Sensing with Charge-Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology

2016 IEEE International Solid-State Circuits Conference (ISSCC)(2016)

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关键词
FinFET CMOS technology,asymmetric sense amplifier,charge-shared bitline,dummy-read disturb,RDWL,read wordline,internal storage nodes,charge-sharing,1R1W,1-read 1-write 8T decoupled dual port cells,read and write disturb issues,2RW,2-read-write 8T dual-port SRAM,multiport memories,IP blocks,SoC designs,system-on-chip designs,size 14 nm
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