Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2020）
关键词
high performance low power logic application,short channel high performance,novel Si-cap-free gate oxide solution,strain relaxed buffer,highly active strained source,nanosheet PMOSFET,gate-all-around strained Si0.40.6 nanosheet PMOS,current 9.1 A,size 5.0 nm,size 25.0 nm,voltage -0.5 V,Si0.7Ge0.3,Si0.4Ge0.6
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